Electronic packaging continues to evolve and impact the electronics industry. The trend toward smaller, lighter, and thinner consumer products requires further packaging improvements. Surface-mount technology (SMT) and ball grid array (BGA) packages allow reduction of pad pitch on the printed circuit board. Chip-scale or chip-size packaging (CSP) includes packages having areas that are little more than the original die area. Wafer-level packaging (WLP) and lead-frame-based CSP are types of CSP.
WLP refers to packaging an integrated circuit at wafer level, instead of assembling the package of each individual unit after wafer dicing. WLP extends the wafer fabrication process to include device connection and device protection processes. Often, in WLP a completely packaged wafer is burned-in and tested after the final packaging step, such that tests before packaging are no longer necessary.
Lead-frame-based CSP refers to packaging semiconductor chips at a lead-frame array packaging level, instead of the traditional process of packaging semiconductor chips one at a time. Lead-frame-based CSP uses wafer level fabrication processes for connecting and protecting devices, which reduces packaging time, inventory and costs.
For these and other reasons, there is a need for the present invention.